EVG Joins European Wafer Stacking Program

EV Group (EVG) joins the 3D integration consortium of IRT Nanoelec headed by CEA-Leti and includes STMicro and Mentor Graphics to develop advanced 3D wafer-to-wafer bonding technologies. SET also joined recently the consortium.

S�verine Ch�ramy, director of the 3D integration program of IRT Nanoelec, said the consortium expects to achieve an interconnection pitch of about 1�m.

"Wafer-to-wafer stacking using direct Cu-to-Cu bonding is key for advanced 3D technologies, specifically for imaging application and 3D partitioning," Ch�ramy said. "EVG's knowledge on bonding will leverage the process expertise of the original members. The participation of EVG in the consortium will create new opportunities and optimized and cost-effective solutions for 3D IC devices."